Experience

 
 
 
 
 

PhD Research Intern

Advanced Micro Devices (AMD)

May 2022 – July 2022 Singapore

  • Research Intern at AMD Xilinx Labs Asia Pacific CTO group.
  • Working on hardware-software accelerator for emerging blochains.
 
 
 
 
 

PhD Research Intern

Renesas

Jan 2022 – April 2022 Singapore

  • Worked on DRP-AI accelerator.
 
 
 
 
 

CPU Design Engineer

Qualcomm

Jul 2018 – Jan 2021 Bengaluru, India
Responsibilities include:

  • Delivering multi-clock domain and Low Power(UPF) RTL delivery of ARM Kryo cores for Snapdragon chipsets
  • Exposure to Power ManagerIP, DCVS and Low Power Modes using ARM’s P-channel, and boot RTL in Snapdragon CPU’s
  • Experienced in writing SystemVerilog assertions, code coverage and functional coverage closure
  • Experienced in Synthesis flows,reviewing Design Constraints, timing arcs, and optimised registers
 
 
 

Research Internship

Nanyang Technological University

Aug 2017 – Dec 2017 Singapore

  • Designed a dynamic memory authentication scheme for cyberphysical systems and improved upon it using cache-oblivious algorithms.
  • The design was initially studied on FPGA's and further integrated in Multi2sim system simulator to study the performance impact with various SPEC and PARSEC benchmarks.
  • Resulted in an average reduction of performance overhead by 20-30%.

Publications

Conferences


DAC

HALO: Hardware-aware Quantization with Low Critical-Path-Delay Weights for LLM Acceleration

Rohan Juneja, Shivam Aggarwal, Safeen Huda, Tulika Mitra, Li-Shiuan Peh

In IEEE Design Automation Conference (DAC) 2025 [Under Review]

ISCA

A Data-Driven Dynamic Execution Orchestration Architecture

Pranav Dangi, Zhenyu Bai, Rohan Juneja, Zhaoying Li, Zhanglu Yan, Huiying Lan, Tulika Mitra

In International Symposium on Computer Architecture (ISCA) 2025 [Under Review]

ISCA

Nexus Machine: An Active Message Inspired Reconfigurable Architecture for Irregular Workloads

Rohan Juneja, Thilini Kaushalya, Pranav Dangi, Zhaoying Li, Tulika Mitra, Li-Shiuan Peh

In International Symposium on Computer Architecture (ISCA) 2025 [Under Review]

ASPLOS

Enhancing CGRA Efficiency through Aligned Compute and Communication Provisioning

Zhaoying Li, Pranav Dangi, Chenyang Yin, Thilini Kaushalya, Rohan Juneja, Cheng Tan, Zhenyu Bai, Tulika Mitra

In International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2025


PACT

ZeD: A Generalized Accelerator for Variably Sparse Matrix Computations in ML

Pranav Dangi, Zhenyu Bai, Rohan Juneja, Dhananjaya Wijerathne, Tulika Mitra

In International Conference on Parallel Architectures and Compilation Techniques (PACT) 2024

DATE

NOVA: NoC-based Vector Unit for Mapping Attention Layers on a CNN Accelerator

Mohit Upadhyay, Rohan Juneja, Weng-Fai Wong, Li-Shiuan Peh

In Design, Automation and Test in Europe Conference (DATE) 2024


ICCAD

FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow

Thilini Kaushalya, Dan Wu, Rohan Juneja, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh

In International Conference on Computer-Aided Design (ICCAD) 2023


DAC

REACT: A Heterogeneous Reconfigurable Neural Network Accelerator with Software Configurable NoCs for Training and Inference on Wearables

Mohit Upadhyay, Rohan Juneja, Bo Wang, Jun Zhou, Weng-Fai Wong, Li-Shiuan Peh

In IEEE Design Automation Conference (DAC) 2022


ASP-DAC

Cache-Aware Dynamic Skewed Tree for Fast Memory Authentication

Saru Vig, Rohan Juneja, Siew Kei Lam

In Asia and South Pacific Design Automation Conference (ASP-DAC) 2021


DATE

DISSECT: Dynamic Skew-and-Split Tree for Memory Authentication

Saru Vig, Rohan Juneja, Siew Kei Lam, Guiyuan Jian

In Design, Automation and Test in Europe Conference (DATE) 2020


ISQED

Dynamic NoC Platform for Varied Application Needs

Sidhartha Shankar, Hemanta K. Mondal, Rohan Juneja, Sri Harsha Gade, Sujay Deb

In International Symposium on Quality Electronic Design (ISQED) 2018

Journals


TRETS

CTScan: A CGRA-based Platform for Emulation of Power Side-Channel Attacks on Edge CPUs

Yaswanth Tavva, Rohan Juneja, Trevor E. Carlson, Li-Shiuan Peh

In ACM Transactions on Reconfigurable Technology and Systems (TRETS) 2025 [Minor Revision]


TVLSI

Framework for Fast Memory Authentication Using Dynamically Skewed Integrity Tree

Saru Vig, Rohan Juneja, Guiyuan Jiang, Siew Kei Lam, Changhai Ou

In IEEE Transactions on Very Large Scale Integration Systems (TVLSI) 2019

Chip Tapeouts


ISOCC

A 360 GOPS/W CGRA in a RISC-V SoC with Multi-Hop Routers and Idle-State Instructions for Edge Computing Applications

Vishnu Nambiar, Yi Sheng Chong, Thilini Kaushalya, Dhananjaya Wijerathne, Zhaoying Li, Rohan Juneja, Li-Shiuan Peh, Tulika Mitra, Anh Tuan Do

In International System-on-Chip Conference (ISOCC 2024)

HotChips

PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications

Vishnu Nambiar, Yi Sheng Chong, Thilini Kaushalya, Dhananjaya Wijerathne, Zhaoying Li, Rohan Juneja, Li-Shiuan Peh, Tulika Mitra, Anh Tuan Do

In Hot Chips Symposium (HotChips 2024)

Contact